1. Field of the Invention
The present invention relates to a method and program for checking the presence/absence of errors in test patterns used in a testing method for detecting manufacture failures in integrated circuits, such as LSIs (large scale integrations).
2. Description of the Related Art
Checking of manufacture failures in LSIs requires a great number of test patterns. When an LSI includes sequence circuit devices, for example, flip flops and/or latches, the complexity of creating the test patterns further increases.
Accordingly, scan design is typically employed for LSIs. In LSIs employing scan design, sequence circuit devices (mainly, flip flops) in each LSI are used to form scan chains, test patterns are shifted in through the scan chains, and the values of the scan chains are read out after clock application.
For example, a failure checking method called “parallel scan chain approach” has been conventionally used for checking manufacture failures in LSIs.
FIG. 1 is a schematic diagram of a parallel scan chain.
An LSI 100 includes a test control circuit 101 and flip flops (FFs) 102, 103, 104, and 105. Multiple flip flops including the flip flops 102 and 103 constitute a scan chain 106 and multiple flip flops including the flip flops 104 and 105 similarly constitute a scan chain 107. In FIG. 1, scan chains other than the scan chains 106 and 107, constituted by flip flops, are also provided in the LSI 100. In the case of a parallel scan chain configuration, up to 16 scan chains are provided. Each scan chain is connected to the test control circuit 101 and LSI external input/output pins.
The parallel scan chains 106 and 107 will be described below for the sake of clarity of the operation of parallel scanning and only associated input/output pins and so on provided externally to the LSI will be described. Other parallel scan chains, which are provided in the LSI 100 but are not illustrated, operate in the same manner as the parallel scan chains 106 and 107, which are described below. This description, therefore, does not intend to mean that the parallel scan chains are limited to two parallel scan chains 106 and 107.
First, all state values in the LSI 100 are set to an indefinite value “X” to perform initialization. Herein, setting to the indefinite value means that whether the initial state values in the LSI 100 take 1 or 0 is unknown. Such setting is necessary for improving the accuracy of checking.
In order to extract information of the parallel scan chains 106 and 107, a test pattern is input from LSI external pins 108 and 109 dedicated to the test circuit 101 to perform simulation and the test control circuit 101 is set to a scan shift state.
The test control circuit 101 includes a scan shift clock generator (not shown), which supplies clock signals, for example, typically, an ACK (A clock) signal and a BCK (B clock) signal, directly to the flip flops to perform simulation and signal paths from scan-in (SI) pins to scan-out (SO) pins of the flip flops 102 to 105 are set to through states.
Since the scan shift clock generator (not shown) is provided in the test control circuit 101 in this case, a simulator can make a determination. The expression “through states” refer to states in which signals 0 or 1 indicating a test pattern pass through the scan flop flops 102 to 105 without inversion. The simulator, which is not shown for simplicity, inputs a test pattern to the LSI 100 to perform simulation.
When values “0” are supplied via the LSI external input pins 108 and 109 of the respective parallel scan chains 106 and 107 to perform simulation, the values “0” pass through the scan flip flops 102 to 105 without change and reach respective LSI external output pins 110 and 111 of the parallel scan chains 106 and 107, due to the through states of the scan flip flops 102 to 105.
During the signal passage, the scan flip flops are sequentially traced to thereby extract data regarding the parallel scan chains.
Thereafter, a test pattern is generated and results output from the external output pins 110 and 11 are read to thereby make it possible to detect an LSI manufacture failure.
FIG. 2 is a schematic diagram of pins of a flip flop 200 to be scanned.
Pins at the input side include a CK pin 201 for receiving a clock signal indicating the timing of data reception, a D pin 202 for receiving data, an SI pin 205 for receiving parallel scan data, and an ACK pin 203 and a BCK pin 204 for receiving signals for shifting the data. Pins at the output side include a Q pin 206 for outputting the data received from the D pin 202 according to the clock signal received via the CK pin 201 and an SO pin 207 for outputting the scan data received via the SI pin 205. Typically, when the shift clock signals are alternately input via the ACK pin 203 and the BCK pin 204 once, the flip flop 200 shifts the parallel scan data.
FIG. 3 is a schematic diagram showing a case in which data regarding parallel scan chains in the related art is extracted.
More specifically, FIG. 3 is an enlarged partial diagram of the parallel scan chain portion (106 or 107) shown in FIG. 1.
Each parallel scan chain is constituted by multiple flip flops, such as flip flops 301, 302, and 303. In this case, flip flops other than the flip flops 301, 302, and 303 may also be provided and the number of flip flops constituting the parallel scan chain is not limited to 3.
With respect to all flip flops constituting the parallel scan chain, the ACK signal and the BCK signal input to the flip flops are turned on and “0” is input to the parallel scan chain via the LSI external input pin to execute simulation. “0” illustrated before each flip flop shown in FIG. 3 indicates that “0” is input to the flip flop and the arrow indicates that “0” is transmitted through the parallel scan chain.
All parallel scan chains are directly connected to the LSI external pins. In the presence of 16 scan chains, the number of LSI external pins provided at each of the input side and the output side is 16.
Thus, when the scan flip flops, which are provided between the LSI external input pins and the LSI external output pins, are traced starting at the LSI external input pins, data regarding all the parallel scan chains can be obtained. The “tracing” herein refers to inputting a test pattern through the external input pins and checking the states of the parallel scan chains.
As related art, Japanese Patent Application Laid-Open No. 2002-236144 discloses a technology in which a pattern modifier that modifies, in response to an external input, a test pattern generated by a pattern modifier and that inputs the modifier test pattern to shift registers. Increasing or reducing the number of scan paths, which are constituted by the shift registers, allows test time for an integrated circuit (e.g., an LSI) to be reduced. In this case, since only significant data portions are supplied from a tester and modified, the amount of data stored in the tester can be reduced.
This arrangement allows high-quality testing to be executed in a short period of time, and allows high-quality testing to be conducted without imposing stringent design restrictions on a designer and without requiring a high-quality tester.
Other than the above-described parallel scanning, BAST (Built-in-scan-test Aided Scan Test) scanning is also available as a scanning method. Unlike the parallel scanning, the BAST scanning allows the provision of a larger number of BAST scan chains than the number of external input/output pins and allows the scanning of a larger number of scan chains than those for the parallel scanning.
However, in an LSI having BAST scan chains, the number of external input pins does not correspond to the number of BAST scan chains and thus a test pattern cannot be transmitted through the LSI external input/output pins, unlike the parallel scan chains. This makes it impossible to easily extract data regarding the scan chains.